An astable
multivibrator (a-stable or not stable) is a type of square wave oscillator. The
following circuit is a classical astable multivibrator. A detailed description
of how it works is related to analog circuits and so will not be discussed here.
In short, capacitors C1 and C2 take turns charging and turning transistors Q1
and Q2 on. When Q1 turns on it forces Q2 off and discharges C2. When Q2 turns on
it forces Q1 off and discharges C1. This continues as long as power is applied
to the circuit.
A classical astable multivibrator. This is an oscillator that produces
square waves.
Monostable
multivibrator
A monostable
multivibrator (aka one-shot) has an output that is normally held at a logical
low. There is a trigger input called the clock that causes the output to go to a
logical high. After a predetermined time the output will automatically go back
to a logical low. The output has two possible states, but it will always return
to the low state. It is only stable in that one state, so it is monostable.
The basic diagram
of a 74121 monostable multivibrator. The circuit is triggered when the
clock input () goes from high to low. The resistor and capacitor determine
how long the Q output remains high before it falls back to low.
Flip-flops (bi-stable
multivibrators)
A bi-stable multivibrator
is the classical "flip-flop." The output of a flip-flop has two possible states
and will not change from one to the other unless it receives a specific command
to do so; it is stable in either of the two states, so it is said to be
bi-stable.
S-R flip-flop
S-R flip-flop will
change its Q output from low to high if the S input is made high. However, when
the S input is changed back to low the output doesn't change back with it.
Repeating the high on the S input will not change the output; it will remain
high. If the R input is made high, the Q output will go from high to low. The Q
output will then remain low until the S input is made high again. In short, a
high signal to the S input (the Set input) will cause the Q output to go high
and a high signal to the R input (the Reset input) will cause the Q output to go
low.
An S-R flip-flop
in the reset state; Q is low (black) and is high (red).
Here the S input
is made high. This forces the bottom gate low which then causes the top
gate to make Q high
When the S input
is made low again, the outputs do not change.
Now the R input is
made high which forces Q low which then causes the bottom gate to make
high. The gate is now in the original state
In the following
circuit, and
are normally held high. When is pulled low the
flip-flop goes into the set state (Q high). When is pulled low the flip goes
into the reset state (Q low).
An S-R flip-flop with
inverted inputs (a-flip-flop).
S-R flip-flops are often
used as switch debounce circuits. Whenever a switch is turned on or off, some
noise generated. This noise causes the switch to appear to turn on and off
several times. This is called switch bounce. This is a significant problem with
certain digital circuits. For example, if a digital counter is used to count how
many times a button is pressed, switch bounce will cause additional erroneous
counts. Using an S-R flip-flop between the switch and the counter will eliminate
the effect of the switch bounce (recall that repeating the input will not change
the output more than once)
Switch debounce circuit
An S-R flip-flop used as
a switch debounce circuit. The switch is an SPDT pushbutton switch. The
resistors hold the inputs high when there is no connection from the switch
(resistors used in this way are called pull-up resistors). When the switch is
pressed, the input is forced to ground (low) which causes Q to go low. Any
switch bounce is ignored. When the switch is released,
is forced low which
returns Q to the high state. Again, any bounce is ignored.
J-K Flip-flop
A J-K flip-flop is a
modified S-R flip-flop where the output doesn't change until a third signal
commands the change. The equivalent of the S input is the J input and the
equivalent of the R input is the K input. If the J input is made high, Q will
not go high until the clock input also goes high. Likewise, making the K input
high will not cause Q to go low until the clock input also goes high.
A J-K flip-flop
A typical J-K flip-flop
uses a "master-slave" configuration where one flip-flop leads to the input of a
second. This causes the output to change when the clock goes from high to low
rather than from low to high. As will be shown later, this is useful in making
counting circuits.
Typical symbol for a master-slave J-K flip-flop
The circle on the clock input (C) denotes that this
is an inverted or negative logic input; the flip-flop changes its output state
when the clock goes from high to low instead of from low to high.
Toggling Flip-flop
If J and K are both held
high, each time the clock signal goes high the output will change (toggle). If Q is high
when the clock goes high, Q will go low and vice versa. If the clock is repeated
over and over, the output will toggle back and forth repeatedly.
D-type flip-flops
A D-Type flip-flop,
also called a latch, is designed to hold data. It is a single-bit memory
circuit. When the clock input goes from high to low the bit at the D input is
transferred to the Q output. After that, the Q output holds that bit until the
clock goes from high to low again. With some D flip-flops, the Q output will
change whenever the D input changes as long as the clock is held high. When the
clock goes low the Q output will hold whatever bit was at the D input at the
time the clock went low.
A D flip-flop made from
a J-K flip-flop and an inverter. The line over the 'C' is another indication
that this is an inverted clock.
There are several ways
to make a D flip-flop. One way is to use a J-K flip-flop with an inverter as
above. The following symbol is used for a straight D flip-flop circuit with no
indication of how it is constructed.
Typical symbol for a D
flip-flop.
D flip-flops often come
in packages with multiple flip-flops with a common clock line. For example, the
74175 is a TTL quad D flip-flop with the following arrangement.
A 74175 quad D flip-flop
(reset inputs not shown).
) goes from high to low. The resistor and capacitor determine
how long the Q output remains high before it falls back to low.
is high (red).
and
are normally held high. When is pulled low the
flip-flop goes into the set state (Q high). When is pulled low the flip goes
into the reset state (Q low).
